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ATCompiler®–Semitronix’s addressable test chip design platform – provides a complete solution for the design of large addressable & scribe line addressable test chips. It offers layout automation, full chip simulation and verification, design documentation and testing program generation on one single platform.

  • Use SRAM-like decoders to select testing structures in the array, where bit cells are replaced by testing patterns;
  • Built-in addressable IP of yield array, transistor array, RO array and CBCM for various processes;
  • High area-efficiency to fulfill the design of experiments with high measurement accuracy;
  • Allow overlapped test structures.


  • Flexible array size as well as tape-out area;
  • Easily placed either in scribe lane or as MPW;
  • DOE table based testing structure automation;
  • Automatic and optimized placing and routing;
  • Full chip LVS and post simulation;
  • Automatic testing program generation & design documentation.


  • Up to 1pA resolution for Ioff and gate leakage current;
  • >10x area efficiency improvement by using much fewer frame pads and by overlapping testing structures in different layers;
  • Complete simulation and verification flow to ensure high quality;
  • Maintain a platform which is stable and independent of 3rd party layout software.

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