SmtCell/TCMagic

Home > Products > SmtCell/TCMagic

Semitronix provides a complete solution for the design of test chips, PCM, SRAM/Flash variants and other IP related structures.

SmtCell:

OVERVIEW:

SmtCell®– Semitronix’s powerful PCell building tool – has the capacity to create almost any kind of parameterized testing structures for foundries, design houses and IDMs; users can easily achieve >10x productivity gain in building SPICE/Reliability/RF/Process/Yield related testing structures such as MOS transistor, inductor, capacitor, resistor, via chain, comb snake, SRAM bit cell etc.

MAIN FEATURES:

  • User friendly GUI for PCell building and editing;
  • Flexible PCell building functions such as attribute, constraint, operation and TCL script;
  • Support more than 20 operations;
  • TCL programming capability;
  • Highly hierarchical PCells and instances for small data size;
  • Built-in verification functions for error checking;
  • Support Linux or Windows OS environment.

MAJOR BENEFITS:

  • No third party software is needed;
  • Greatly reduce human labor for layout creation;
  • Error free designs can be achieved easily;
  • Easy and fast migration from one technology node to another.
Download booklet



TCMagic:

OVERVIEW:

TCMagic®–Semitronix’s test chip design platform – provides a complete solution for the design of scribe line and MPW test chips. It offers layout automation, design documentation and testing program generation on one single platform.

MAIN FEATURES:

  • Extensive built-in PCells, including all common PCM structures and yield related testing structures;
  • Compatible with PCells built by SmtCell® or Skill based PCells;
  • DOE based testing structure automation;
  • Template and table based placing and routing to create modules;
  • Automatic design documentation;
  • Automatic testing program generation;
  • Comprehensive design verifications, including integrations of 3rd party DRC and LVS toolsC, structure level pin connection check, and routing connection check, etc.

MAJOR BENEFITS:

  • Improve layout efficiency by at least 10X;
  • Reduce human errors and human labors significantly;
  • Shorten development time of testing program;
  • Easy and fast migration from one technology node to another;
  • Maintain a platform which is stable and independent of other layout engines.

Module GDSII Creation


Copyright© Semitronix Corporation  2013-2015 All Rights Reserved