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Millions DUTs/die and 40,000 DUTs/sec --- Semitronix Releases Latest Ultra-dense and Ultra-fast Dense Array Technology Time:2018-04-04 Click:4197

Recently, Semitronix' Dense Array technology has been successfully taped-out and silicon verified at multiple leading semiconductor IDM and foundries.

The Dense Array technology is an innovative ultra-high-density test chip with ultra-fast wafer-level measurement technology; it is especially suitable for the development and production ramp of advanced semiconductor technologies (such as with HKMG and FinFET elements). Through rigorous research and extensive simulation and silicon verification in the past two years by Semitronix R&D team, it is able to accommodate millions DUTs in a single test chip die; and moreover, tens of thousands of DUTs can be tested in a second, enabling a complete test chip solution for process development and yield improvement at advanced semiconductor processes.

Dense Array Test Chip Layout

With the shrink of the integrated circuit and continuation of Moore's law, IC chip’s integration level increased ten million times in the last 60 years. However, IC performance, power and cost as its core competitiveness needs to maintain and improve with new technology innovations. This poses a huge challenge for process technology owners to develop and bring-up leading edge technologies. Accompanying these innovations, new physical issues needs to be fully characterized and vetted within the limited test site reticle area. Even if high area utilization can be achieved in test chip design, the ability to extract silicon data at a reasonable speed still inhibits the effectiveness of such solutions. Thus, ultra-high density and high speed test chip solution becomes an urgent challenge for the industry.

To address this challenge, Semitornix’ Dense Array technology composes not only ultra-high-density test chip design, but also the proprietary test method and systems to achieve rapid test of high-density designs. The specific technical specifications are as follows:

l > 1million DUTs in a test chip, and rapid test system to test these DUTs.

l Demonstrated density of DUT is 10 ~ 25um2 per DUT. A ~10mm2 test chip can accommodate one million DUTs.

l Flexible support of DUTs, including, but not limited to standard cell library devices, SRAM devices Pcell based devices and others.

l Demonstrated the test speed of up to 40,000 DUTs/s. (single bias condition).

l Measurement accuracy down to ~ 10nA.

l Test items include Idsat, Ioff and I-V curve.

l Support two test modes: continuous fast test and pinpoint DUT test.

l only two metal layers required for design.

l Both open/short hard defects and outliers can be detected.

Schematic of Dense Array Test Chip and Test System

Test Data (dark spots are outliers)

I-V Curve Comparison

The Dense Array technology has been verified and implemented at many of our world-leading customers, and have completed silicon validation. It is recognized as a key enabler for our customers to drive future research and development of advanced technologies. For Semitronix, the Dense Array technology marks a breakthrough in test chip technology to address product yield and performance issues. It complements our existing test site infra-structures that have been widely adopted in the industry.

About us:

Semitronix is a leading provider of characterization and yield improvement solutions encompassing software, hardware, and services for the semiconductor industry. Semitronix’ proven solutions cover from 180nm to 7nm technologies. For Foundry, we support full technology life-cycle (from R&D to mass production) characterization test chip needs, from early stage initial designs, mid-late stage addressable high volume test keys, to product specific debug test chip during yield ramp. For Design House, we provide customized test chip solutions to help design houses improve IC design for manufacturability, performance, yield and time to market.