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In order to facilitate robust and high quality production, semiconductor manufacturers utilize test chips to evaluate and monitor their processes.  These test chips contain a plurality of test keys that monitor the health of the process.  These test keys can be tested by test equipment (parametric testers) through the connecting pads.

TCMagic® - Semitronix’s test chip design platform - provides a complete solution for the design of scribe-line, short-flow and MPW test chips.  It offers layout automation, automatic place-and-routing, design documentation and testing program generation on one unified platform.


•  Extensive built-in PCells, including all common PCM structures and yield related testing keys
•  Supports exported PCells from SmtCell®
•  DOE based testing key instantiation
•  Template and table-based placement & routing to create testable modules
•  Automatic design documentation generation
•  Automatic testing program generation
• Comprehensive design error checks including built-in DRC, link to 3rd party DRC, structure level pin connection check, and routing connection check


•  Improves layout efficiency by at least 10X
•  Significantly reduces human errors and human labor
•  Shortens development time of down-stream documentation and test program generation
•  Easy and fast migration from one technology node to another
•  Maintains a platform which is stable and independent of the layout engineers

Main GUI

Module GDSII Creation