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Semitronix provides advanced addressable solution for test chips.  With addressable designs, area requirement for test chip is significantly reduced due to pad sharing, while simultaneously providing test speed up with reduced probing requirement.

The addressable solution includes two components: addressable IPs and addressable test chip design platform (ATCompiler).

Addressable IPs include our proprietary peripheral circuits (addressing circuit/signal selection circuit, switching circuit, and etc.).  Semitronix has developed a variety of IPs (respectively for yield, transistor, capacitance and etc.) to support a broad range of test keys and measurement types.
• Technology-customized & silicon-proven addressable IPs for test chip design efficiency
• Optimized measuring circuits in addressable IPs to ensure the highly accurate measurement results
• Four major classes of IPs available for parametric & yield analyses, and measurement on transistors, ring oscillators and capacitances

ATCompiler® - Semitronix’s addressable test chip design platform - provides a complete solution for the design of large addressable & scribe line addressable test chips.  It offers full addressable layout automation, simulation, verification, design documentation and testing program generation on one unified platform.
● Supports of PCell based test keys
● Supports custom-layout such as product block weak-spot and/or std-cell devices
● Allows overlapped test keys



Addressable Yield IP

Addressable Yield Test Chip