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With ever increasing complexity of semiconductor process, the need for test keys to monitor these processes also grows.  The wafer area required to support these test keys becomes impractical.  Addressable test chip technology offers a solution that drastically reduces area requirement while even speeding up the test.

ATCompiler® - Semitronix’s addressable test chip design platform - supports various DC/AC parametric measurements.  It provides a complete solution for the design of large addressable & scribe line addressable test chips.  It offers full layout automation, test-key generation, place-and-routing, design simulation and verification, design documentation and testing program generation on one unified platform.

• Automated addressable test chip design, supporting full range of Semitronix addressable IPs
• Test key generation supporting both PCell based designs and fully customized designs
• Automated supporting of product-based weak-spots, devices in standard cell libraries and functional blocks
• High quality design ensured by both built-in and linked 3-rd party DRC/LVS, connectivity checks
• Supports stacked test key placement for optimal design densityMAIN FEATURES • Flexible array size as well as tape-out area
• Easily placed either in scribe lane or as MPW
• DOE table based testing key automation
• Automatic and optimized placing and routing
• Full chip LVS and post simulation
• Automatic testing program generation & design documentation
MAJOR BENEFITS • Up to 1pA resolution for Ioff and gate leakage current
• >10x area efficiency improvement by using much fewer frame pads and by overlapping testing keys in different layers
• Complete simulation and verification flow to ensure high quality
• Maintains a platform which is stable and independent of 3rd party layout software

GUI of ATCompiler®

Diagram of Generating Addressable Test Chip

As part of ATCompiler®, Addressable IPs include peripheral circuits (addressing circuit/signal selection circuit, switching circuit, etc.) and pads.  Semitronix provides different IP types to support different test structure types in ATCompiler®.

• Integrate the addressable method into IP design to save the area of pads
• Assist users to design test chip efficiently by providing the required addressable IP instead of spending times to design the required IP
• Optimize the peripheral circuit of addressable IP to ensure the high precision of measuring results
• Provide four available types of IP for yield, transistors, ring oscillators and capacitors